The Gate Driver on Array (GOA) technology integrates a Thin Film Transistor (TFT) working as a gate switch circuit on an array substrate, thereby saving the gate driving IC and reducing product cost in terms of material cost and process steps.
A GOA-based gate switch circuit TFT is generally formed on the array substrate at the same time with TFTs in pixel regions. Moreover, TFTs of various sizes are formed in the GOA element. TFTs of various sizes specifically refer to the formed TFTs having channels of different sizes. In a source/drain tied (SDT) device (that is a semiconductor active layer and a source/drain electrode layer are formed through a single patterning process), transmittance of a Half Tone Mask (HTM) used in an ashing process for the source/drain electrode is varied according to the TFT size. Variation in the transmittance of the HTM causes TFT channel locations to have different photoresist thickness during the ashing process, which eventually will break TFT channel regions having relatively thin photoresist after the subsequent etching is done and leave the TFTs open-circuited.
As shown in FIGS. 1 and 2, configurations of two bottom gate TFTs are schematically illustrated. The two TFTs have similar configuration and are formed according to the same procedure which comprises the steps of sequentially forming a gate electrode P2, a gate insulating layer (not shown in the figures), an active layer P3 as well as a source/drain (S/D) metal layer P4 on a substrate P1 from the bottom up, then forming a channel region using HTM technology, that is, forming a first photoresist P5 on the S/D metal layer P4, after being exposed and developed using the HTM, forming a first photoresist aperture region P6 above the S/D metal layer P4 at a position where the channel region to be formed. A part of the photoresist leaves in the aperture region P6. However, photoresist in the first photoresist aperture region of the TFT structure in FIG. 1 has a thickness of h1, while photoresist in the first photoresist aperture region of the TFT structure in FIG. 2 has a thickness of h2, and h1<h2. Since hl is relatively small, the photoresist can not completely protect the source/drain metal layer in the channel region of FIG. 1. Specifically, in FIG. 1, when the left photoresist in the first photoresist aperture region P6 is exposed and developed to form a source electrode and a drain electrode, the thickness of the photoresist in the aperture region P6 is reduced to a certain extent. When the photoresist is further exposed, developed and etched to form the channel region, the active layer P3 will be partly etched due to the photoresist is relatively thin. When channel region is fanned for the TFT of FIG. 1, the actively layer is partly etched, which will cause the channel region to break; as a result, the TFT switch is open-circuited and a defect is generated.
FIG. 5 schematically illustrates a configuration of a top-gate TFT which is similar to the configuration illustrated in FIG. 1. In the TFT, a channel region is also easily broken due to a photoresist in a first photoresist aperture region P6′ above a S/D metal layer P4′ for forming the channel region has a relatively small thickness h1, which will make the TFT switch open-circuited and cause a defect.